Configurable low-latency low power video processing architecture for star-tracking based LEO navigation systems

Description

Satellite navigation systems require low power and low latency tracking devices. The guidance of satellites uses, in addition to GPS receivers, alternative mechanisms based on images named star tracking. Data-stream computing cannot be efficiently performed by general purpose processors GPPs in terms of both power consumption and computing performance. Specialized processors such as ASICs (Application Specific Integrated Circuits) are optimized to provide the best performance but at a high development cost and flexibility restrictions. A pure software solution, while flexible, doesn’t provide the power processing required by LEO satellites. Parallel processing from SIMD architectures are also not an appropriate alternative due to the high power consumption and inherent data dependencies. In real-time embedded systems, these parameters are crucial, especially in latency-critical applications that must quickly react to incoming events. A coursegrained systolic architecture named P2IP was already developed to support a basic set of image processing operators easily configurable and driven by a software application. The architecture combines minimal latency, low power, high performance and short compilation times. P2IP can achieve up to 121fps in Full HD 1080p and 30 fps in 4K 2160p in an FPGA-based implementation making it suitable for modern high-definition applications. In this context, the objectives of the thesis will be to evaluate existing star tracking algorithms in terms of processing power, complexity, memory requirements and power consumption and to propose a novel approach capable to extend P2IP for star tracking applications. A set of required optimized course-grain operators will be developed to support the configurable functionality that will be needed by the software application.